1. Field of the Invention
This invention relates to a memory apparatus, a memory controlling method and a program having a replacement processing function for replacing a memory cell which suffers from an error with another memory cell in a replacement area.
2. Description of the Related Art
Verify reading after writing or erasure of data into or from memory cells of a volatile or nonvolatile memory which allows electric writing or erasure is carried out to carry out a series of controlling processes of verifying whether or not writing or erasure has been carried out correctly.
FIG. 1 illustrates a processing flow of a writing process into memory cells.
Referring to FIG. 1, the memory apparatus first carries out writing into a memory cell at step ST1 and then carries out verification at step ST2, whereafter it carries out a comparison process between the read out data and the write data at step ST3.
If the data coincide with each other as a result of the comparison process, then the processing is ended, but if the data do not coincide with each other, then the processing steps beginning with step ST1 are repeated by a designated number of times until it is detected at step ST4 that the data coincide with each other.
Similar processing is carried out also in the case of erasure.
In this manner, the memory apparatus repeats the series of controlling operations by a predetermined number of times until writing or erasure is carried out correctly. If coincide of data is not detected with a memory cell even if the series of controlling operations is repeated by more than the predetermined number of times, then it is decided that the memory cell is a defective memory cell whose characteristic has changed or deteriorated.
As a result, a notification of an error of the writing or erasure process is sent to a controller.
Incidentally, it is popular with regard to volatile memories and nonvolatile memories to carry out a replacement process for an initial defective memory cell which is found in an inspection.
A technique for a nonvolatile memory ready for a replacement process for a defective memory cell which is found also upon writing is proposed, for example, in Japanese Patent Application No. 2007-518819 and Japanese Patent Laid-Open Nos. Hei 9-128962, Hei 8-031190 and Hei 8-007597.
FIG. 2 illustrates a flow of operations of a replacement process proposed already.
Replacement processes used in the techniques disclosed in the documents mentioned above commonly include such steps as seen in FIG. 2.
It is to be noted that, in the following description, a defective memory cell is sometimes referred to as defective cell and an alternate memory cell is sometimes referred to as replacement cell.
Referring to FIG. 2, at first step ST11, a replacement cell which can be used alternately and is not used as yet in a replacement area is determined from the address of a defective cell.
Then at second step ST12, data which should originally be written into the defective cell is written into the replacement cell and it is confirmed that the writing is completed normally.
Then at third step ST13, it is confirmed whether or not an error has occurred.
If an error has occurred, then it is determined at fourth step ST14 that also the replacement cell is a defective cell and should be inhibited from being used, and the replacement process is ended as an error and, when a replacement process is started again, this is retried with another replacement cell.
On the other hand, if no error has occurred and the writing is completed normally, then it is stored at fifth step ST15 that accessing to the defective cell upon address decoding should be changed over to accessing to the replacement cell, and the replacement process is completed therewith.